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CY14MB064J2A Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY14MB064J2A Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 28 page  CY14MB064J1A/CY14MB064J2A CY14ME064J1A/CY14ME064J2A Document Number: 001-70393 Rev. *I Page 11 of 28 Current nvSRAM Read Each read operation starts with the master transmitting the nvSRAM slave address with the LSB set to ‘1’ to indicate “Read”. The reads start from the address on the address counter. The address counter is set to the address location next to the last accessed with a “Write” or “Read” operation. The master may terminate a read operation after reading 1 byte or continue reading addresses sequentially until the last address in the memory after which the address counter rolls back to the address 0x0000. The valid methods of terminating read access are described in the section Read Operation on page 10. Figure 12. Single-Byte Write into nvSRAM (Hs-mode) S0 0 0 0 1X X X A A A A S T A R T Memory Slave Address Most Significant Address Byte Least Significant Address Byte Hs-mode command SDA Line By Master A S T 0 P P Data Byte Sr 10 1 0 A2 A1 A0 0 By nvSRAM XX X Figure 13. Multi-Byte Write into nvSRAM (Hs-mode) S0 0 0 0 1X X X A A A A S T A R T Memory Slave Address Most Significant Address Byte Least Significant Address Byte Hs-mode command SDA Line By Master A Data Byte 1 Sr 10 1 0 A2 A1 A0 0 A Data Byte 2 A Data Byte 3 A S T 0 P P Data Byte N By nvSRAM SDA Line By Master By nvSRAM XX X Figure 14. Current Location Single-Byte nvSRAM Read (except Hs-mode) S1 0 1 0 A2 A1 A0 1 A A S T A R T S T 0 P P Data Byte Memory Slave Address SDA Line By Master By nvSRAM |
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