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CY14B256PA-SFXI Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY14B256PA-SFXI Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 43 page  CY14C256PA CY14B256PA CY14E256PA Document Number: 001-65281 Rev. *G Page 11 of 43 Write Protection and Block Protection CY14X256PA provides features for both software and hardware write protection using WRDI instruction and WP. Additionally, this device also provides block protection mechanism through BP0 and BP1 pins of the Status Register. The write enable and disable status of the device is indicated by WEN bit of the Status Register. The write instructions (WRSR, WRITE, WRTC and WRSN) and nvSRAM special instruction (STORE, RECALL, ASENB, ASDISB) need the write to be enabled (WEN bit = ‘1’) before they can be issued. Write Enable (WREN) Instruction On power-up, the device is always in the write disable state. The following WRITE, WRSR, WRTC, WRSN or nvSRAM special instruction must therefore be preceded by a Write Enable instruction. If the device is not write enabled (WEN = ‘0’), it ignores the write instructions and returns to the standby state when CS is brought HIGH. A new CS falling edge is required to re-initiate serial communication. The instruction is issued following the falling edge of CS. When this instruction is used, the WEN bit of Status Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up. Note After completion of a write instruction (WRSR, WRITE, WRTC or WRSN) or nvSRAM special instruction (STORE, RECALL, ASENB, ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to provide protection from any inadvertent writes. Therefore, WREN instruction needs to be used before a new write instruction is issued. Figure 6. Read Status Register (RDSR) Instruction Timing Figure 7. Fast Read Status Register (FAST_RDSR) Instruction Timing CS SCK SO 0123456 7 SI 0000 0 1 0 0 1 HI-Z 0 12345 6 7 Data LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 Op-Code CS SCK SO 0123456 7 SI 0000 1 0 0 1 HI-Z 8 9 10 11 12 13 14 15 0 Data LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 X X X X X X X X Dummy Byte 0 12345 6 7 Op-Code Figure 8. Write Status Register (WRSR) Instruction Timing CS SCK SO 0 1 2 3 4567 SI 0000 0 0 0 1 MSB LSB D2 D3 D7 HI-Z 0 12345 67 Opcode Data in X X X X X |
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