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CY8C20436AN-24LQXI Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY8C20436AN-24LQXI Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 51 page CY8C20XX6A/S Document Number: 001-54459 Rev. *T Page 10 of 51 24-pin QFN (17 Sensing Inputs) [7] Table 2. Pin Definitions – CY8C20336A, CY8C20346A, CY8C20346AS [8] Pin No. Type Name Description Figure 3. CY8C20336A, CY8C20346A, CY8C20346AS Digital Analog 1 I/O I P2[5] Crystal output (XOut) 2 I/O I P2[3] Crystal input (XIn) 3 I/O I P2[1] 4 IOHR I P1[7] I2C SCL, SPI SS 5 IOHR I P1[5] I2C SDA, SPI MISO 6 IOHR I P1[3] SPI CLK 7 IOHR I P1[1] ISSP CLK[9], I2C SCL, SPI MOSI 8 NC No connection 9 Power VSS Ground connection 10 IOHR I P1[0] ISSP DATA[9], I2C SDA, SPI CLK[10] 11 IOHR I P1[2] 12 IOHR I P1[4] Optional external clock input (EXTCLK) 13 IOHR I P1[6] 14 Input XRES Active high external reset with internal pull-down 15 I/O I P2[0] 16 IOH I P0[0] 17 IOH I P0[2] 18 IOH I P0[4] 19 IOH I P0[6] 20 Power VDD Supply voltage 21 IOH I P0[7] 22 IOH I P0[5] 23 IOH I P0[3] Integrating input 24 IOH I P0[1] Integrating input CP Power VSS Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. QF N (T op V ie w ) AI, I2C SCL , SPI SS , P 1 [7 ] AI, I2 C SDA, SPI M ISO , P 1 [5 ] AI, SPI C LK , P 1 [3 ] 1 2 3 4 5 6 18 17 16 15 14 13 P 0 [2 ], A I P 0 [0 ], A I P 0[4], A I A I, P 2 [1 ] P 1[6], A I XR E S P 2[0], A I A I, X O u t, P 2 [5] A I, XIn , P2[3 ] Notes 7. 20 GPIOs = 17 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor. 8. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 9. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 10. Alternate SPI clock. |
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