ST72F521R6TA datasheet(67/215 Pages) STMICROELECTRONICS

Part #	ST72F521R6TA

Description	80/64-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

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ST72F521, ST72521B

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PWM AUTO-RELOAD TIMER (Cont’d)

PWM CONTROL REGISTER (PWMCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = OE[3:0] PWM Output Enable

These bits are set and cleared by software. They

enable or disable the PWM output channels inde-

pendently acting on the corresponding I/O pin.

0: PWM output disabled.

1: PWM output enabled.

Bit 3:0 = OP[3:0] PWM Output Polarity

These bits are set and cleared by software. They

independently select the polarity of the four PWM

output signals.

Note: When an OPx bit is modified, the PWMx out-

put signal polarity is immediately reversed.

DUTY CYCLE REGISTERS (PWMDCRx)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = DC[7:0] Duty Cycle Data

These bits are set and cleared by software.

A PWMDCRx register is associated with the OCRx

register of each PWM channel to determine the

second edge location of the PWM signal (the first

edge location is common to all channels and given

by the ARTARR register). These PWMDCR regis-

ters allow the duty cycle to be set independently

for each PWM channel.

70

OE3

OE2

OE1

OE0

OP3

OP2

OP1

OP0

PWMx output level

OPx

Counter <= OCRx

Counter > OCRx

10

0

01

1

70

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

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