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CY14B256Q1 Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY14B256Q1 Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 29 page  CY14B256Q1 CY14B256Q2 CY14B256Q3 Document Number: 001-53882 Rev. *J Page 8 of 29 are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of the first bit (MSB) of SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK. Data Transmission - SI and SO SPI data bus consists of two lines, SI and SO, for serial data communication. The SI is also referred to as Master Out Slave In (MOSI) and SO is referred to as Master In Slave Out (MISO). The master issues instructions to the slave through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO lines as described earlier. CY14B256Q1/CY14B256Q2/CY14B256Q3 has two separate pins for SI and SO, which can be connected with the master as shown in Figure 4 on page 8. Most Significant Bit (MSB) The SPI protocol requires that the first bit to be transmitted is the most significant bit (MSB). This is valid for both address and data transmission. The 256-Kbit serial nvSRAM requires a 2-byte address for any read or write operation. However, since the address is only 15-bits, it implies that the first MSB that is fed in is ignored by the device. Although this bit is ‘don’t care’, Cypress recommends that this bit is treated as 0 to enable seamless transition to higher memory densities. Serial Opcode After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the intended operation. CY14B256Q1/CY14B256Q2/CY14B256Q3 uses the standard opcodes for memory accesses. In addition to the memory accesses, it provides additional opcodes for the nvSRAM specific functions: STORE, RECALL, AutoStore Enable, and AutoStore Disable. Refer to Table 2 on page 10 for details. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI pin till the next falling edge of CS and the SO pin remains tristated. Status Register CY14B256Q1/CY14B256Q2/CY14B256Q3 has an 8-bit Status Register. The bits in the Status Register are used to configure the SPI bus. These bits are described in the Table 4 on page 11. Figure 4. System Configuration Using SPI nvSRAM x Q 6 5 2 B 4 1 Y C x Q 6 5 2 B 4 1 Y C uC o ntrolle r SC K MO S I MIS O SI SO O S I S K C SS C K CS HO L D HO L D CS CS 1 CS 2 HO L D 1 HO L D 2 |
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