CY8C20XX6A/S

Document Number: 001-54459 Rev. *T

Page 9 of 51

Pinouts

The CY8C20XX6A/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables. Every

not capable of Digital I/O.

16-pin QFN (10 Sensing Inputs)[3, 4]

Table 1. Pin Definitions – CY8C20236A, CY8C20246A, CY8C20246AS PSoC Device

Pin

No.

Type

Name

Description

Figure 2. CY8C20236A, CY8C20246A, CY8C20246AS

Digital

Analog

1

I/O

I

P2[5] Crystal output (XOut)

2

I/O

I

P2[3] Crystal input (XIn)

3

IOHR

I

4

IOHR

I

5

IOHR

I

P1[3] SPI CLK

6

IOHR

I

MOSI

7

Power

Ground connection

8

IOHR

I

CLK[6]

9

IOHR

I

P1[2]

10

IOHR

I

P1[4] Optional external clock

(EXTCLK)

11

Input

XRES Active high external reset with

internal pull-down

12

IOH

I

P0[4]

13

Power

Supply voltage

14

IOH

I

P0[7]

15

IOH

I

P0[3] Integrating input

16

IOH

I

P0[1] Integrating input

LEGEND

A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

QFN

( Top View)

AI, XOut, P2[5]

AI,I2 C SCL, SPI SS, P1[7]

AI,I2 C SDA, SPI MISO, P1[5]

1

2

3

4

11

10

9

P0[4] , AI

P1[2] , AI

AI, XIn, P2[3]

P1[4] , EXTCLK, AI

XRES

12

Notes

3. 13 GPIOs = 10 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.

4. No Center Pad.

5. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

6. Alternate SPI clock.