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CY8C24894 Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8C24894 Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 65 page  CY8C24094, CY8C24794 CY8C24894, CY8C24994 Document Number: 38-12018 Rev. AG Page 3 of 65 4. PSoC Functional Overview The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture, shown in “Logic Block Diagram” on page 1, consists of four main areas: the core, the system resources, the digital system, and the analog system. Configurable global bus resources allow combining all of the device resources into a complete custom system. Each CY8C24x94 PSoC device includes four digital blocks and six analog blocks. Depending on the PSoC package, up to 56 GPIOs are also included. The GPIOs provide access to the global digital and analog interconnects. 4.1 The PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (IMO) and internal low-speed oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-million instructions per second (MIPS) 8-bit Harvard-architecture microprocessor. System resources provide these additional capabilities: ■ Digital clocks for increased flexibility ■ I 2C functionality to implement an I2C master and slave ■ An internal voltage reference, multi-master, that provides an absolute value of 1.3 V to a number of PSoC subsystems ■ A switch-mode pump (SMP) that generates normal operating voltages from a single battery cell ■ Various system resets supported by the M8C The digital system consists of an array of digital PSoC blocks that may be configured into any number of digital peripherals. The digital blocks are connected to the GPIOs through a series of global buses. These buses can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller. The analog system consists of six analog PSoC blocks, supporting comparators, and analog-to-digital conversion up to 10-bits of precision. 4.2 The Digital System The digital system consists of four digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Digital peripheral configurations include: ■ PWMs (8- to 32-bit) ■ PWMs with dead band (8- to 32-bit) ■ Counters (8- to 32-bit) ■ Timers (8- to 32-bit) ■ UART 8-bit with selectable parity ■ SPI master and slave ■ I 2C slave and multi-master ■ CRC/generator (8-bit) ■ IrDA ■ PRS generators (8- to 32-bit) The digital blocks are connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 5. Figure 1. Digital System Block Diagram DIGITAL SYSTEM To System Bus Digital Clocks From Core Digital PSoC Block Array To Analog System 8 8 8 8 Row 0 DBB00 DBB01 DCB02 DCB03 4 4 GIE[7:0] GIO[7:0] GOE[7:0] GOO[7:0] Global Digital Interconnect Port 1 Port 0 Port 3 Port 2 Port 5 Port 4 Port 7 |
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