CY8C21345

CY8C22345

CY8C22545

Document Number: 001-43084 Rev. *Q

Page 9 of 39

CY8C22545 44-pin TQFP

Table 3. Pin Definitions

Pin No.

Type

Pin Name

Description

Figure 4. Pin Diagram

Digital

Analog

1

I/O

ML

P2[5]

Optional ADC External Vref

2

I/O

ML

P2[3]

3

I/O

ML

P2[1]

4

Power

Vdd

Supply Voltage

5

I/O

ML

P4[5]

6

I/O

ML

P4[3]

7

I/O

ML

P4[1]

8

Power

Vss

Ground Connection

9

I/O

ML

10

I/O

ML

11

I/O

ML

12

I/O

ML

13

I/O

ML

P1[7]

I2C serial clock (SCL)

14

I/O

ML

P1[5]

I2C serial data (SDA)

15

I/O

ML

P1[3]

16

I/O

ML

P1[1]

Crystal (XTALin), I2C SCL, TC SCLK[4]

17

Power

Vss

Ground Connection

18

I/O

MR

P1[0]

Crystal (XTALout), I2C SDA, TC

SDATA[4

]

19

I/O

MR

P1[2]

20

I/O

MR

P1[4]

Optional external clock input (EXTCLK)

21

I/O

MR

P1[6]

22

I/O

MR

P3[0]

23

I/O

MR

P3[2]

24

I/O

MR

P3[4]

25

I/O

MR

P3[6]

26

Input

XRES

Active High Pin Reset with Internal Pull

Down

27

I/O

MR

P4[0]

28

I/O

MR

P4[2]

29

I/O

MR

P4[4]

30

Power

Vss

Ground Connection

31

I/O

MR

P2[0]

32

I/O

MR

P2[2]

33

I/O

MR

P2[4]

34

I/O

I, MR

P2[6]

To Compare Column 1

35

I/O

I, MR

P0[0]

36

I/O

I, MR

P0[2]

37

I/O

I, MR

P0[4]

38

I/O

I, MR

P0[6]

39

Power

Vdd

Supply Voltage

40

I/O

I, MR

P0[7]

Integration Capacitor for MR

41

I/O

I, ML

P0[5]

Integration Capacitor for ML

42

I/O

I, ML

P0[3]

43

I/O

I, ML

P0[1]

44

I/O

I, ML

P2[7]

To Compare Column 0

LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input.

ADC_Ext_Vref, ML, P2[5]

ML, P2[3]

ML, P2[1]

Vdd

TQFP

1

2

3

4

5

6

7

8

24

23

31

30

29

28

27

26

P2[0], MR

XRES

P2[4], MR

11

10

9

25

32

33

ML, P4[5]

ML, P4[3]

ML, P4[1]

ML, P3[7]

ML, P3[5]

ML, P3[3]

P3[2], MR

P3[4], MR

P3[6], MR

P4[0], MR

P4[2], MR

P4[4], MR

Vss

P2[2], MR

Vss