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CY8C20140 Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY8C20140 Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 46 page CY8C20110, CY8C20180 CY8C20160, CY8C20140 CY8C20142 Document Number: 001-54606 Rev. *J Page 7 of 46 Figure 6. Circuit 3 – Compatibility with 1.8 V I2C Signaling [8, 9] Figure 7. Circuit 4 – Powering Down CapSense Express Device for Low Power Requirements [10] Typical Circuits (continued) Master Or Host LDO CapSense Express I2C Pull UPs LED I2C BUS SDA SCL VDD Output Output enable Notes 8. 1.8 V VDD_I2C VDD_CE and 2.4 V VDD_CE 5.25 V. 9. The I2C drive mode of the CapSense device should be configured properly before using in an I2C environment with external pull-ups. Please refer to I2C_ADDR_DM register and its factory setting. 10. For low power requirements, if VDD is to be turned off, this concept can be used. The requirement is that the VDDs of CapSense Express, I2C pull-ups, and LEDs should be from the same source such that turning off the VDD ensures that no signal is applied to the device while it is unpowered. The I2C signals should not be driven high by the master in this situation. If a port pin or group of port pins of the master can cater to the power supply requirements of the circuit, the LDO can be avoided. |
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