CY8C20xx7/S

Document Number: 001-69257 Rev. *I

Page 7 of 43

Pinouts

The CY8C20x37/47/67/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables.

are not capable of digital I/O.

16-pin SOIC (10 Sensing Inputs)

Table 1. Pin Definitions – CY8C20237-24SXI, CY8C20247/S-24SXI [4]

Pin

No.

Type

Name

Description

Figure 2. CY8C20237-24SXI, CY8C20247/S-24SXI

Device

Digital

Analog

1

I/O

I

P0[3] Integrating Input

2

I/O

I

P0[1] Integrating Input

3

I/O

I

P2[5] Crystal output (XOut)

4

I/O

I

P2[3] Crystal input (XIn)

5

I/O

I

P1[7] I2C SCL, SPI SS

6

I/O

I

P1[5] I2C SDA, SPI MISO

7

I/O

I

P1[3]

8

I/O

I

MOSI

9

Power

10

I/O

I

CLK[6]

11

I/O

I

P1[2] Driven Shield Output (optional)

12

I/O

I

P1[4] Optional external clock

(EXTCLK)

13

INPUT

XRES Active high external reset with

internal pull-down

14

I/O

I

P0[4]

15

Power

16

I/O

I

P0[7]

LEGEND

A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

SOIC

P0[7], AI

P0[4], AI

XRES

P1[4], EXTCLK

P1[2], AI

16

15

14

13

12

11

1

2

3

4

5

6

7

8

AI, P0[3]

AI, P0[1]

AI, P2[5]

AI, P2[3]

AI, P1[7]

AI, P1[5]

AI, P1[3]

10

9

Notes

5. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

6. Alternate SPI clock.