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CY8C5668LTI-LP014 Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY8C5668LTI-LP014 Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 120 page  PSoC® 5LP: CY8C56LP Family Datasheet Programmable System-on-Chip (PSoC®) Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-84935 Rev. *C Revised March 8, 2013 General Description With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing MCU, memory, analog, and digital peripheral functions in a single chip. The CY8C56LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C56LP family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C56LP family is also a high performance configurable digital system with some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN). In addition to communication interfaces, the CY8C56LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core. You can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C56LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. Features 32-bit ARM Cortex-M3 CPU core DC to 67 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles, 20 year retention, and multiple security features Up to 32-KB flash error correcting code (ECC) or configuration storage Up to 64 KB SRAM 2-KB electrically erasable programmable read-only memory (EEPROM) memory, 1 M cycles, and 20 years retention 24-channel direct memory access (DMA) with multilayer AHB[1] bus access • Programmable chained descriptors and priorities • High bandwidth 32-bit transfer support Low voltage, ultra low power Wide operating voltage range: 0.5 V to 5.5 V High efficiency boost regulator from 0.5 V input to 1.8 V to 5.0 V output 3.1 mA at 6 MHz Low-power modes including: • 2 µA sleep mode with real time clock and low voltage detect (LVD) interrupt • 300 nA hibernate mode with RAM retention Versatile I/O system 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs[2]) Any GPIOs to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46 × 16 segments CapSense® support from any GPIO[3] 1.2 V to 5.5 V I/O interface voltages, up to four domains Maskable, independent IRQ on any pin or port Schmitt-trigger TTL inputs All GPIOs configurable as open drain high/low, pull-up/pull-down, High Z, or strong output Configurable GPIO pin state at power-on reset (POR) 25 mA sink on SIO Digital peripherals 20 to 24 programmable PLD based universal digital blocks (UDB) Full CAN 2.0b 16 RX, 8 TX buffers[2] Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator[2] Four 16-bit configurable timer, counter, and PWM blocks 67-MHz, 24-bit fixed point digital filter block (DFB) to implement FIR and IIR filters Library of standard peripherals • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs • Serial peripheral interface (SPI), universal asynchronous transmitter receiver (UART), I2C • Many others available in catalog Library of advanced peripherals • Cyclic redundancy check (CRC) • Pseudo random sequence (PRS) generator • LIN bus 2.0 • Quadrature decoder Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V) 1.024 V±0.1% internal voltage reference across –40 °C to +85 °C Configurable delta-sigma ADC with 8- to12-bit resolution[2] • Programmable gain stage: ×0.25 to ×16 • 12-bit mode, 192-ksps, 66-dB signal to noise and distortion ratio (SINAD), ±1-bit INL/DNL Up to two SAR ADCs, each 12-bit at 1 Msps Four 8-bit 8 Msps IDACs or 1 Msps VDACs Four comparators with 95 ns response time Four uncommitted opamps with 25 mA drive capability Four configurable multifunction analog blocks. Example configurations are PGA, TIA. Mixer and sample and hold CapSense support Programming, debug, and trace JTAG (4 wire), serial-wire debug (SWD) (2 wire), single-wire viewer (SWV), and TRACEPORT interfaces Cortex-M3 flash patch and breakpoint (FPB) block Cortex-M3 Embedded Trace Macrocell™ (ETM™) generates an instruction trace stream. Cortex-M3 data watchpoint and trace (DWT) generates data trace information Cortex-M3 Instrumentation Trace Macrocell (ITM) can be used for printf-style debugging DWT, ETM, and ITM blocks communicate with off-chip debug and trace systems via the SWV or TRACEPORT Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces Precision, programmable clocking 3 to 62 MHz internal oscillator over full temperature and voltage range 4 to 25 MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 67 MHz 32.768-kHz watch crystal oscillator Low-power internal oscillator at 1, 33, and 100 kHz Temperature and packaging –40 °C to +85 °C degrees industrial temperature 68-pin QFN and 100-pin TQFP package options Notes 1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information on page 113 for details. 3. GPIOs with opamp outputs are not recommended for use with CapSense. |
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