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CY8C20237-24LKXI Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY8C20237-24LKXI Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 43 page CY8C20xx7/S Document Number: 001-69257 Rev. *I Page 11 of 43 32-pin QFN (25 Sensing Inputs)[18] Table 5. Pin Definitions – CY8C20437, CY8C20447/S, CY8C20467/S [19] Pin No. Type Name Description Figure 6. CY8C20437, CY8C20447/S, CY8C20467/S Device Digital Analog 1 IOH I P0[1] Integrating input 2 I/O I P2[5] Crystal output (XOut) 3 I/O I P2[3] Crystal input (XIn) 4 I/O I P2[1] 5 I/O I P4[3] 6 I/O I P3[3] 7 I/O I P3[1] 8 IOHR I P1[7] I2C SCL, SPI SS 9 IOHR I P1[5] I2C SDA, SPI MISO 10 IOHR I P1[3] SPI CLK. 11 IOHR I P1[1] ISSP CLK[20], I2C SCL, SPI MOSI. 12 Power VSS Ground connection 13 IOHR I P1[0] ISSP DATA[20], I2C SDA, SPI CLK[21] 14 IOHR I P1[2] Driven Shield Output (optional) 15 IOHR I P1[4] Optional external clock input (EXTCLK) 16 IOHR I P1[6] 17 Input XRES Active high external reset with internal pull-down 18 I/O I P3[0] 19 I/O I P3[2] 20 I/O I P4[0] 21 I/O I P4[2] 22 I/O I P2[0] 23 I/O I P2[2] Driven Shield Output (optional) 24 I/O I P2[4] Driven Shield Output (optional) 25 IOH I P0[0] Driven Shield Output (optional) 26 IOH I P0[2] Driven Shield Output (optional) 27 IOH I P0[4] 28 IOH I P0[6] 29 Power VDD 30 IOH I P0[7] 31 IOH I P0[3] Integrating input 32 Power VSS Ground connection CP Power VSS Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. AI ,P0[1] AI ,P2[5] AI , XOut ,P2[3] AI , XIn ,P2[1] AI ,P4[3] AI ,P3[3] QFN (Top View) 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 AI ,P3[1] AI ,I2 C SCL, SPI SS,P1[7] P2[4] ,AI P2[2] ,AI P3[0] ,AI XRES P2[0] ,AI P4[2] ,AI P4[0] ,AI P3[2] ,AI Notes 18. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 19. 28 GPIOs = 25 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor. 20. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 21. Alternate SPI clock. |
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