REV. A

AD9847

–4–

TIMING SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Unit

MASTER CLOCK (CLI)

CLI Clock Period

25

ns

CLI High/Low Pulsewidth

12.5

ns

Delay from CLI to Internal Pixel

Period Position

6ns

EXTERNAL MODE CLAMPING

CLPDM Pulsewidth

410Pixels

CLPOB Pulsewidth

*

220

Pixels

SAMPLE CLOCKS

SHP Rising Edge to SHD Rising Edge

10

ns

DATA OUTPUTS

Output Delay from Programmed Edge

6ns

Pipeline Delay

9

Cycles

SERIAL INTERFACE

Maximum SCK Frequency

10

MHz

SL to SCK Setup Time

10

ns

SCK to SL Hold Time

10

ns

SDATA Valid to SCK Rising Edge Setup

10

ns

SCK Falling Edge to SDATA Valid Hold

10

ns

SCK Falling Edge to SDATA Valid Read

10

ns

*Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.

Specifications subject to change without notice.