CY7C25632KV18

CY7C25652KV18

Document Number: 001-66482 Rev. *D

Page 6 of 31

Functional Overview

The CY7C25632KV18, CY7C25652KV18 are synchronous

pipelined Burst SRAMs equipped with a read port and a write

port. The read port is dedicated to read operations and the write

port is dedicated to write operations. Data flows into the SRAM

through the write port and flows out through the read port. These

devices multiplex the address inputs to minimize the number of

address pins required. By having separate read and write ports,

the QDR II+ completely eliminates the need to “turn-around” the

data bus and avoids any possible data contention, thereby

simplifying system design. Each access consists of four 18-bit

data transfers in the case of CY7C25632KV18, and four 36-bit

data transfers in the case of CY7C25652KV18, in two clock

cycles.

These devices operate with a read latency of two and half cycles

when DOFF pin is tied HIGH. When DOFF pin is set LOW or

read latency of one clock cycle.

Accesses for both ports are initiated on the positive input clock

(K). All synchronous input and output timing are referenced from

the rising edge of the input clocks (K and K).

controlled by the input clocks (K and K). All synchronous data

by the rising edge of the input clocks (K and K) as well.

through input registers controlled by the rising edge of the input

clocks (K and K).

CY7C25632KV18 is described in the following sections. The

same basic descriptions apply to CY7C25652KV18.

Read Operations

The CY7C25632KV18 is organized internally as four arrays of

1 M × 18. Accesses are completed in a burst of four sequential

18-bit data words. Read operations are initiated by asserting

RPS active at the rising edge of the positive input clock (K). The

address presented to the address inputs is stored in the read

address register. Following the next two K clock rise, the

corresponding lowest order 18-bit word of data is driven onto the

subsequent rising edge of K, the next 18-bit data word is driven

valid 0.45 ns from the rising edge of the input clock (K or K). To

maintain the internal logic, each read access must be allowed to

complete. Each read access consists of four 18-bit data words

and takes two clock cycles to complete. Therefore, read

accesses to the device can not be initiated on two consecutive

K clock rises. The internal logic of the device ignores the second

read request. Read accesses can be initiated on every other K

clock rise. Doing so pipelines the data flow such that data is

transferred out of the device on every rising edge of the input

clocks (K and K).

When the read port is deselected, the CY7C25632KV18 first

completes the pending read transactions. Synchronous internal

circuitry automatically tri-states the outputs following the next

rising edge of the negative input clock (K). This enables for a

seamless transition between devices without the insertion of wait

states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the

rising edge of the positive input clock (K). On the following K

DOFF

Input

PLL Turn Off

 Active LOW. Connecting this pin to ground turns off the PLL inside the device. The

timings in the PLL turned off operation differs from those listed in this data sheet. For normal operation,

this pin can be connected to a pull up through a 10 k

 or less pull up resistor. The device behaves in

QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up

to 167 MHz with QDR I timing.

TDO

Output

TDO Pin for JTAG.

TCK

Input

TCK Pin for JTAG.

TDI

Input

TDI Pin for JTAG.

TMS

Input

TMS Pin for JTAG.

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/144M

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/288M

N/A

Not Connected to the Die. Can be tied to any voltage level.

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

Power Supply Power Supply Inputs to the Core of the Device.

Ground

Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

Pin Name

I/O

Pin Description