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CY7C67200-48BAXIT Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C67200-48BAXIT Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 92 page  CY7C67200 Document Number: 38-08014 Rev. *I Page 9 of 92 Operational Modes There are two modes of operation: Coprocessor and Stand- alone. Coprocessor Mode EZ-OTG can act as a coprocessor to an external host processor. In this mode, an external host processor drives EZ-OTG and is the main processor rather then EZ-OTG’s own 16-bit internal CPU. An external host processor may interface to EZ-OTG through one of the following three interfaces in coprocessor mode: ■ HPI mode, a 16-bit parallel interface with up to 16 MBytes transfer rate ■ HSS mode, a serial interface with up to 2M baud transfer rate ■ SPI mode, a serial interface with up to 2 Mbits/s transfer rate. At bootup GPIO[31:30] determine which of these three interfaces are used for coprocessor mode. Refer to Table 14 for details. Bootloading begins from the selected interface after POR + 3 ms of BIOS bootup. Standalone Mode In standalone mode, there is no external processor connected to EZ-OTG. Instead, EZ-OTG’s own internal 16-bit CPU is the main processor and firmware is typically downloaded from an EEPROM. Optionally, firmware may also be downloaded via USB. Refer to Table 14 for booting into standalone mode. After booting into standalone mode (GPIO[31:30] = ‘11’), the fol- lowing pins are affected: ■ GPIO[31:30] are configured as output pins to examine the EEPROM contents. ■ GPIO[28:27] are enabled for debug UART mode. ■ GPIO[29] is configured as OTGID for OTG applications on PORT1A. ❐ If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral. ❐ If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host. ■ Ports 1B, 2A, and 2B default as USB peripheral ports. ■ All other pins remain INPUT pins. Minimum Hardware Requirements for Standalone Mode – Peripheral Only Figure 5. Minimum Standalone Hardware Configuration – Peripheral Only EZ-OTG CY7C67200 GPIO[30] GPIO[31] SCL* SDA* 10k Bootstrap Options Bootloading Firmware *Bootloading begins after POR + 3ms BIOS bootup Vcc 10k Vcc A2 GND A0 A1 SCL SDA VCC WP VCC Up to 64k x8 EEPROM *GPIO[31:30] 31 30 Up to 2k x8 SCL SDA >2k x8 to 64k x8 SDA SCL Int. 16k x8 Code / Data XOUT XIN 12MHz 22pf 22pf nRESET Reset Logic * Parallel Resonant Fundamental Mode 500uW 20-33pf ±5% VCC, AVCC, BoostVCC VReg DMinus DPlus Standard-B or Mini-B D+ VBus GND D- SHIELD Reserved GND, AGND, BoostGND |
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