CY7C1470V33

CY7C1472V33

CY7C1474V33

Document Number: 38-05289 Rev. *S

Page 11 of 38

Truth Table

The Truth Table for parts CY7C1470V33/CY7C1472V33/CY7C1474V33 is as follows. [5, 6, 7, 8, 9, 10, 11]

Operation

DQ

Deselect cycle

None

H

L

L

X

X

X

L

L–H

Tri-state

Continue deselect cycle

None

X

L

H

X

X

X

L

L–H

Tri-state

Read cycle (begin burst)

External

L

L

L

H

X

L

L

L–H Data out (Q)

Read cycle (continue burst)

Next

X

L

H

X

X

L

L

L–H Data out (Q)

NOP/dummy read (begin burst)

External

L

L

L

H

X

H

L

L–H

Tri-state

Dummy read (continue burst)

Next

X

L

H

X

X

H

L

L–H

Tri-state

Write cycle (begin burst)

External

L

L

L

L

L

X

L

L–H

Data in (D)

Write cycle (continue burst)

Next

X

L

H

X

L

X

L

L–H

Data in (D)

NOP/write abort (begin burst)

None

L

L

L

L

H

X

L

L–H

Tri-state

Write abort (continue burst)

Next

X

L

H

X

H

X

L

L–H

Tri-state

Ignore clock edge (stall)

Current

X

L

X

X

X

X

H

L–H

–

Sleep mode

None

X

H

X

XXXX

X

Tri-state

Notes

5. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = 0 signifies at least one byte write select is active, BWx = valid signifies

that the desired byte write selects are asserted, see Write Cycle Description table for details.

7. When a write cycle is detected, all I/Os are tristated, even during byte writes.

8. The DQ and DQP pins are controlled by the current cycle and the OE signal.

9. CEN = H inserts wait states.

10. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE.