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CY7C1470V33-167AXI Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C1470V33-167AXI Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 38 page CY7C1470V33 CY7C1472V33 CY7C1474V33 Document Number: 38-05289 Rev. *S Page 9 of 38 Functional Overview The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are synchronous-pipelined burst NoBL SRAMs designed specifically to eliminate wait states during write/read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0 ns (200 MHz device). Accesses can be initiated by asserting all three chip enables (CE1, CE2, CE3) active at the rising edge of the clock. If clock enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the write enable (WE). BW[x] can be used to conduct byte write operations. Write operations are qualified by the write enable (WE). All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD should be driven LOW after the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, (3) the write enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.0 ns (200 MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (read/write/deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tristate following the next clock rise. Burst Read Accesses The CY7C1470V33, CY7C1472V33, and CY7C1474V33 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Accesses section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, TMS Test mode select synchronous This pin controls the test access port state machine. Sampled on the rising edge of TCK. TCK JTAG clock Clock input to the JTAG circuitry. VDD Power supply Power supply inputs to the core of the device. VDDQ I/O power supply Power supply for the I/O circuitry. VSS Ground Ground for the device. Should be connected to ground of the system. NC – No connects. This pin is not connected to the die. NC (144M, 288M, 576M, 1G) – These pins are not connected. They will be used for expansion to the 144M, 288M, 576M, and 1G densities. ZZ[4] Input- asynchronous ZZ “Sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Pin Definitions (continued) Pin Name I/O Type Pin Description Note 4. Errata: The ZZ pin needs to be externally connected to ground. For more information, see Errata on page 34. |
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