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CY7C1470BV33-167AXC Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1470BV33-167AXC
Description  72-Mbit (2 M x 36/4 M 횞 18/1 M x 72) Pipelined SRAM with NoBL??Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1470BV33-167AXC Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Document Number: 001-15031 Rev. *K
Page 8 of 34
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK.
BWa, BWb,
BWc, BWd,
BWe, BWf,
BWg, BWh
Input-
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf,
BWg controls DQg and DQPg, BWh controls DQh and DQPh.
WE
Input-
Synchronous
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input Used to Advance the On-chip Address Counter or Load a New Address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to
load a new address.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
Input-
Synchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select or deselect the device.
CE2
Input-
Synchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select or deselect the device.
CE3
Input-
Synchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select or deselect the device.
OE
Input-
Asynchronous
Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control
the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
Input-
Synchronous
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
DQS
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd
are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQX. During write
sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled
by BWg, DQPh is controlled by BWh.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE must not change states during operation. When left floating
MODE defaults HIGH, to an interleaved burst order.
TDO
JTAG Serial
Output
Synchronous
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
TDI
JTAG Serial
Input
Synchronous
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.


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