CY7C1470BV25-167BZXI datasheet(11/29 Pages) CYPRESS

Part #	CY7C1470BV25-167BZXI

Description	72-Mbit (2 M x 36/4 M x 18) Pipelined SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C1470BV25

CY7C1472BV25

Document Number: 001-15032 Rev. *K

Page 11 of 29

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1470BV25 incorporates a serial boundary scan test

access port (TAP). This port operates in accordance with IEEE

Standard 1149.1-1990 but does not have the set of functions

required for full 1149.1 compliance. These functions from the

IEEE specification are excluded because their inclusion places

an added delay in the critical speed path of the SRAM. Note that

the TAP controller functions in a manner that does not conflict

with the operation of other devices using 1149.1 fully compliant

TAPs. The TAP operates using JEDEC-standard 2.5 V I/O logic

levels.

The CY7C1470BV25 contains a TAP controller, instruction

register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may

alternately be connected to VDD through a pull up resistor. TDO

must be left unconnected. During power up, the device comes

up in a reset state, which does not interfere with the operation of

the device.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to leave

this ball unconnected if the TAP is not used. The ball is pulled up

internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers

and can be connected to the input of any of the registers. The

register between TDI and TDO is chosen by the instruction that

is loaded into the TAP instruction register. For information about

loading the instruction register, see the TAP Controller State

Diagram. TDI is internally pulled up and can be unconnected if

the TAP is unused in an application. TDI is connected to the most

significant bit (MSB) of any register.

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current state

of the TAP state machine (see Identification Codes on page 16).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

Performing a TAP RESET

A RESET is performed by forcing TMS HIGH (VDD) for five rising

edges of TCK. This RESET does not affect the operation of the

SRAM and may be performed while the SRAM is operating.

During power up, the TAP is reset internally to ensure that TDO

comes up in a High Z state.

TAP Registers

Registers are connected between the TDI and TDO balls to scan

the data in and out of the SRAM test circuitry. Only one register

can be selected at a time through the instruction register. Data is

serially loaded into the TDI ball on the rising edge of TCK. Data

is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the TDI

and TDO balls as shown in the TAP Controller Block Diagram on

page 14. During power up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as described

in the previous section.

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary ‘01’ pattern to enable fault

isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

register is a single-bit register that can be placed between the

TDI and TDO balls. This shifts the data through the SRAM with

minimal delay. The bypass register is set LOW (VSS) when the

BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR state

and is then placed between the TDI and TDO balls when the

controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used to

capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the bits

are connected. Each bit corresponds to one of the bumps on the

SRAM package. The MSB of the register is connected to TDI and

the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in Identification Register Definitions on

page 16.

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in Identification

Codes on page 16. Three of these instructions are listed as

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CY7C1470BV25-167BZXI Datasheet(PDF) 11 Page - Cypress Semiconductor

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