CY7C1441AV25

CY7C1447AV25

Document Number: 001-75380 Rev. *B

Page 8 of 33

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. Maximum access delay from the

The

CY7C1441AV25/CY7C1447AV25 supports secondary

cache in systems utilizing either a linear or interleaved burst

sequence. The interleaved burst order supports Pentium and

i486™ processors. The linear burst sequence is suited for

processors that utilize a linear burst sequence. The burst order

is user selectable and is determined by sampling the MODE

input. Accesses are initiated with either ADSP or ADSC. Address

advancement through the burst sequence is controlled by the

ADV input. A two-bit on-chip wraparound burst counter captures

the first address in a burst sequence and automatically

increments the address for the rest of the burst access.

Byte write operations are qualified with the Byte Write Enable

Enable (GW) overrides all byte write inputs and writes data to all

four bytes. All writes are simplified with on-chip synchronous self

timed write circuitry.

asynchronous output enable (OE) provide for easy bank

HIGH.

Single Read Accesses

A single read access is initiated when the following conditions

active and (2) ADSP or ADSC is asserted LOW (if the access is

initiated by ADSC, the write inputs must be deasserted during

this first cycle). The address presented to the address inputs is

latched into the address register and the burst counter or control

logic and presented to the memory core. If the OE input is

asserted LOW, the requested data is available as the data

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are

and (2) ADSP is asserted LOW. The addresses presented are

loaded into the address register and the burst inputs (GW, BWE,

inputs are asserted active (see Truth Table on page 10 for

appropriate states that indicate a write) on the next clock rise, the

appropriate data is latched and written into the device. Byte

writes are allowed. All I/Os are tri-stated during a byte write.

Because this is a common I/O device, the asynchronous OE

input signal must be deasserted and the I/Os must be tri-stated

prior to the presentation of data to DQs. As a safety precaution,

the data lines are tri-stated when a write cycle is detected,

regardless of the state of OE.

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are

active, (2) ADSC is asserted LOW, (3) ADSP is deasserted

indicate a write access. ADSC is ignored if ADSP is active LOW.

The addresses presented are loaded into the address register

and the burst counter or control logic and delivered to the

the specified address location. Byte writes are allowed. All I/Os

are tri-stated when a write is detected, even a byte write.

Because this is a common I/O device, the asynchronous OE

input signal must be deasserted and the I/Os must be tri-stated

prior to the presentation of data to DQs. As a safety precaution,

Ground

Ground for the Core of the Device.

I/O Ground Ground for I/O Circuitry.

TDO

JTAG Serial

Output

Synchronous

Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature is

not utilized, this pin should be left unconnected.

TDI

JTAG Serial

Input

Synchronous

Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not utilized,

TMS

JTAG Serial

Input

Synchronous

Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not utilized,

TCK

JTAG-

Clock

NC

–

No Connects. Not internally connected to the die.

NC/72M,

NC/144M,

NC/288M,

NC/576M,

NC/1G

–

No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M, and NC/1G

are address expansion pins and are not internally connected to the die.

Name

I/O

Description