CY7C1350G

Document Number: 38-05524 Rev. *N

Page 8 of 22

Truth Table

The Truth Table for part CY7C1350G is as follows. [4, 5, 6, 7, 8, 9, 10]

Operation

DQ

Deselect cycle

None

H

L

L

X

X

X

L

L–H

Tristate

Continue deselect cycle

None

X

L

H

X

X

X

L

L–H

Tristate

Read cycle (begin burst)

External

L

L

L

H

X

L

L

L–H Data out (Q)

Read cycle (continue burst)

Next

X

L

H

X

X

L

L

L–H Data out (Q)

NOP/dummy read (begin burst)

External

L

L

L

H

X

H

L

L–H

Tristate

Dummy read (continue burst)

Next

X

L

H

X

X

H

L

L–H

Tristate

Write cycle (begin burst)

External

L

L

L

L

L

X

L

L–H

Data in (D)

Write cycle (continue burst)

Next

X

L

H

X

L

X

L

L–H

Data in (D)

NOP/WRITE ABORT (begin burst)

None

L

L

L

L

H

X

L

L–H

Tristate

WRITE ABORT (continue burst)

Next

X

L

H

X

H

X

L

L–H

Tristate

IGNORE CLOCK EDGE (stall)

Current

X

L

X

X

X

X

H

L–H

–

SNOOZE MODE

None

X

H

X

XXXX

X

Tristate

Notes

4. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies

that the desired byte write selects are asserted, see Write Cycle Description table for details.

6. When a write cycle is detected, all DQs are tri-stated, even during byte writes.

7. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

8. CEN = H, inserts wait states.

9. Device will power-up deselected and the DQs in a tristate condition, regardless of OE.