CY7C1350G

Document Number: 38-05524 Rev. *N

Page 5 of 22

Pin Definitions

Name

I/O

Description

Input-

synchronous

Address inputs used to select one of the 128 K address locations. Sampled at the rising edge of

Input-

synchronous

Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising

edge of CLK.

WE

Input-

synchronous

Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal

must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

synchronous

Advance/load input. Used to advance the on-chip address counter or load a new address. When HIGH

(and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be

loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to

load a new address.

CLK

Input-clock

Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is

only recognized if CEN is active LOW.

Input-

synchronous

Input-

synchronous

Input-

synchronous

OE

Input-

asynchronous

Output enable, asynchronous input, active LOW. Combined with the synchronous logic block inside

the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as

outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during

the data portion of a write sequence, during the first clock when emerging from a deselected state, when

the device has been deselected.

CEN

Input-

synchronous

Clock enable input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.

When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,

CEN can be used to extend the previous cycle when required.

ZZ[3]

Input-

asynchronous

ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with

data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an

internal pull-down.

DQs

I/O-

synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the

a write sequence, during the first clock when emerging from a deselected state, and when the device is

deselected, regardless of the state of OE.

I/O-

synchronous

MODE

Input

strap pin

Mode input. Selects the burst order of the device. When tied to GND selects linear burst sequence.

Power supply Power supply inputs to the core of the device.

I/O power

supply

Power supply for the I/O circuitry.

Ground

Ground for the device.

NC

–

No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are address

expansion pins in this device and will be used as address pins in their respective densities.

Note