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CY7C1351G-100AXC Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7C1351G-100AXC
Description  4-Mbit (128 K x 36) Flow-Through SRAM with NoBL??Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1351G-100AXC Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY7C1351G
Document Number: 38-05513 Rev. *M
Page 5 of 21
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
synchronous
Address inputs used to select one of the 128 K address locations. Sampled at the rising edge of
the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:D]
Input-
synchronous
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
edge of CLK.
WE
Input-
synchronous
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
synchronous
Advance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
(and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
Input-
synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2,
and CE3 to select/deselect the device.
CE2
Input-
synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select/deselect the device.
CE3
Input-
synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
OE
Input-
asynchronous
Output enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
Input-
synchronous
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
ZZ[2]
Input-
asynchronous
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with data
integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an internal
pull-down.
DQs
I/O-
synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and
DQP[A:D] are placed in a tristate condition. The outputs are automatically tristated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
DQP[A:D]
I/O-
synchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
sequences, DQP[A:D] is controlled by BW[A:D] correspondingly.
MODE
Input
strap pin
Mode input. Selects the burst order of the device. When tied to GND selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
VDD
Power supply Power supply inputs to the core of the device.
VDDQ
I/O power
supply
Power supply for the I/O circuitry.
VSS
Ground
Ground for the device.
NC
No connects. Not Internally connected to the die.
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 18.


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