CY7C1327G

Document Number: 38-05519 Rev. *M

Page 10 of 23

6 ns cycle,

166 MHz

–240

mA

7.5 ns cycle,

133 MHz

–225

mA

Automatic CE power-down

current – TTL inputs

6 ns cycle,

166 MHz

–100

mA

7.5 ns cycle,

133 MHz

–90

mA

Automatic CE power-down

current – CMOS inputs

f = 0

All speeds

–

40

mA

Automatic CE power-down

current – CMOS inputs

6 ns cycle,

166 MHz

–85

mA

7.5 ns cycle,

133 MHz

–75

mA

Automatic CE power-down

current – TTL inputs

All speeds

–

45

mA

Over the Operating Range

Description

Test Conditions

Min

Max

Unit

Capacitance

Parameter [11]

Description

Test Conditions

100-pin TQFP

Max

Unit

Input capacitance

5pF

Clock input capacitance

5pF

Input/output capacitance

5pF

Thermal Resistance

Parameter [11]

Description

Test Conditions

100-pin TQFP

Package

Unit



JA

Thermal resistance

(junction to ambient)

Test conditions follow standard test methods and

procedures for measuring thermal impedance, per

EIA/JESD51.

30.32

°C/W



JC

Thermal resistance

(junction to case)

6.85

°C/W

Note

11. Tested initially and after any design or process change that may affect these parameters.