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CY7C1325H-133AXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1325H-133AXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 21 page  CY7C1325H 4-Mbit (256 K × 18) Flow-Through Sync SRAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-86114 Rev. ** Revised February 20, 2013 4-Mbit (256 K × 18) Flow-Through Sync SRAM Features ■ 256 K × 18 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ■ 6.5 ns (133 MHz version) ■ Provide high performance 2-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self timed write ■ Asynchronous output enable ■ Available in Pb-free 100-pin TQFP package ■ “ZZ” sleep mode option Functional Description The CY7C1325H is a 256 K × 18 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2 bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:B], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. The CY7C1325H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). The CY7C1325H operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSC CE 1 OE SENSE AMPS MEMORY ARRAY ADSP OUTPUT BUFFERS INPUT REGISTERS MODE CE 2 CE 3 GW BWE A 0,A1,A BW B BW A DQ B,DQP B WRITE REGISTER DQ A,DQP A WRITE REGISTER ENABLE REGISTER A[1:0] DQs DQP A DQP B DQ B,DQP B WRITE DRIVER DQ A,DQP A WRITE DRIVER SLEEP CONTROL ZZ Logic Block Diagram |
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