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UC2874N-2 Datasheet(PDF) 7 Page - Texas Instruments |
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UC2874N-2 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 12 page 7 UC1874-1,-2 UC2874-1,-2 UC3874-1,-2 VSNS pin through an external voltage divider. The differ- ence between the voltage at VSNS and the internal ref- erence level at the non-inverting input is amplified by the voltage amplifier and applied to the non-inverting input of the current amplifier. This instantaneous reference level forms the current command input for the average current control loop. The average current amplifier develops the duty cycle command signal by integrating the current feedback signal with respect to the instantaneous current command input. This output is compared to the fixed high amplitude oscillator ramp waveform at the inputs of the PWM comparator to develop duty cycle information for the PWM drive. The large amplitude oscillator ramp provides both high noise margin and built-in slope com- pensation in average current mode control methodology. The fixed frequency oscillator is programmed with a sin- gle external capacitor connected between CT and GND, and is capable of switching frequencies up to 300kHz. The UC3874 can be synchronized to an external clock by capacitively coupling the signal to the junction of the capacitor at CT and a low value resistor tied to GND. Re- fer to Application Note U-111. The PWM drive signal is applied to the complementary output driver stages. Since the high side switch is an N- channel MOSFET, a means for driving its gate above VCC is required. This is accomplished via the internal 11V regulator and an external capacitor (CBST). CBST is charged through an external diode to VCC or CAP when the low side MOSFET is on. The charging level on Cbst is internally regulated to 11V minus an external diode drop by the UC3874 as long as VCC is above 11V. When the low side MOSFET turns off, CBST is applied across the gate to the source of the upper MOSFET allowing it to begin turn-on. As the upper MOSFET turns on, it lifts or bootstraps the low end of CBST, along with its source. Shortly thereafter, the source voltage level is reduced by RDS(on) · Iload below VCC. When VCC < 10V, Vgs for the high side MOSFET is approximately equal to VCC. If VCC < 8V, logic level MOSFETs are recommended. In these applications, CAP should be shorted to VCC and an external Schottky diode is connected between CAP/VCC and BOOT. For low battery applications, a syn- chronous regulator must be capable of LDO or 100% duty cycle operation. The UC3874 includes circuitry to insure that this mode of operation is possible even though it uses a bootstrapped drive technique for the high side MOSFET. During commanded 100% duty cycle operation, the UC3874 monitors the Vgs drive signal ap- plied to the high side MOSFET, and automatically pro- vides complementary pulses to refresh the bootstrap capacitor when this voltage falls below a set threshold. In this way, near 100% duty cycle operation is possible, with effective duty cycle dependent only upon the value of CBST. High efficiency is obtained primarily by the low side MOSFET which replaces the Schottky diode in the stan- dard buck configuration. Its low Rds(on) produces a much lower voltage drop than a low VF Schottky diode. As output voltages get lower, these improvements be- come more evident. Additional efficiency improvements at light regulator load currents are obtained by automatic switchover to standby mode. In standby mode, the UC3874 disables its MOSFET drivers and oscillator sav- ing both quiescent supply current consumption and more importantly MOSFET gate drive charge current. Standby mode is initiated when the output inductor current has dropped to a user programmable fraction of the designed full load current. Programmability is easily attained by setting the SB pin to a voltage level between 0V and 1V, which corresponds to 50% to 0% of the peak load cur- rent. In this manner, the user can accurately determine when standby mode is initiated, giving the flexibility to di- rectly shape the efficiency vs. load curve. In standby mode, all output current requirements are handled by the output capacitor. Since the output capacitor isn’t being refreshed by the PWM converter, the output voltage will decay at a rate determined by the load current and the output capacitor value: dV dT I C LOAD OUT = Normal operation returns when the output voltage has decayed by approximately 1% from its nominal value. Standby operation can be easily disabled by connecting the SB pin directly to VREF. Another efficiency consid- eration is the the possibility of reverse current in the out- put inductor. For a non-synchronous regulator this isn’t a problem since the diode will block reverse current, allow- ing discontinuous inductor current operation at light loads. Since the synchronous regulator replaces the di- ode with a switch, reverse current can and will flow if the low side switch is on when the inductor is depleted. The UC3874 includes circuitry to prevent reverse current from flowing in the inductor by disabling the low side gate drive signal during discontinuous mode operation. This increases efficiency by eliminating unnecessary I2R losses in the MOSFET and the inductor. Soft start is recommended for Buck converters to reduce stress on the power components during startup, and to reduce overshoot of the output voltage. This improves reliability. The UC3874 includes a user programmable soft start pin to implement this feature. An internal 10mA current source charges the external soft start capacitor which provides a clamp at the output of the voltage |
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