TPS54311, TPS54312

TPS54313, TPS54314

TPS54315, TPS54316

SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005

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5

PIN ASSIGNMENTS

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

AGND

VSENSE

NC

PWRGD

BOOT

PH

PH

PH

PH

PH

RT

FSEL

SS/ENA

VBIAS

VIN

VIN

VIN

PGND

PGND

PGND

PWP PACKAGE

(TOP VIEW)

NC − No internal connection

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.

DESCRIPTION

AGND

1

Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and

FSEL pin. Make PowerPAD connection to AGND.

BOOT

5

Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-side FET driver.

FSEL

19

Frequency select input. Provides logic input to select between two internally set switching frequencies.

NC

3

No connection

PGND

11−13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the

input and output supply returns, and negative terminals of the input and output capacitors.

PH

6−10

Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.

PWRGD

4

SS/ENA is low or internal shutdown signal active.

RT

20

SS/ENA

18

Slow-start/enableinput/output. Dual function pin which provides logic input to enable/disable device operation and capacitor

input to externally set the start-up time.

VBIAS

17

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high

quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.

VIN

14−16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device

package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.

VSENSE

2

Error amplifier inverting input. Connect directly to output voltage sense point.