N25Q128A11B1241F datasheet(30/185 Pages) MICRON

Part #	N25Q128A11B1241F

Description	128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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Manufacturer	MICRON [Micron Technology]

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Operating features

N25Q128 - 1.8 V

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This is followed by the internal Program cycle (of duration tPP).

To spread this overhead, the Quad Command Page Program (QCPP) instruction allows up

to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are

in consecutive addresses on the same page of memory.

For optimized timings, it is recommended to use the QCPP instruction to program all

consecutive targeted bytes in a single sequence versus using several QCPP sequences

with each containing only a few bytes. See Table 33.: AC Characteristics.

The QCPP instruction is transmitted across 4 data lines except when VPP is raised to

VPPH.

The VPP can be raised to VPPH to decrease programming time (provided that the bit 3 of

the VECR has been set to 0 in advance). When bit 3 of VECR is set to 0 after the Quad

Command Page Program instruction sequence has been received, the memory temporarily

goes in Extended SPI protocol, and is possible to perform polling instructions (checking the

WIP bit of the Status Register or the Program/Erase Controller bit of the Flag Status

Register) or Program/Erase Suspend instruction even if DQ2 is temporarily used in this VPP

functionality. The memory automatically comes back in QIO-SPI protocol as soon as the

VPP pin goes Low.

5.3.4

Subsector Erase, Sector Erase and Bulk Erase

Similar to the Extended SPI protocol, Subsector Erase (SSE)(1), the Sector Erase (SE) and

the Bulk Erase (BE) instructions are used to erase the memory in the QIO-SPI protocol.

These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE).

The Erase instruction must be preceded by a Write Enable (WREN) instruction.

The erase instructions are transmitted across 4 data lines unless the VPP is raised to

VPPH.

The VPP can be raised to VPPH to decrease erasing time, provided that the bit 3 of the

VECR has been set to 0 in advance. In this case, after the erase instruction sequence has

been received, the memory temporarily goes in extended SPI protocol, and it is possible to

perform polling instructions (checking the WIP bit of the Status Register or the

Program/Erase Controller bit of the Flag Status Register) or Program/Erase Suspend

instruction even if DQ2 is temporarily used in this VPP functionality. The memory

automatically comes back in QIO-SPI protocol as soon as the VPP pin goes Low.

Note:

Subsector Erase is only available on the 8 Bottom (Top) boot sectors, and is not available in

uniform architecture parts

5.3.5

Polling during a Write, Program or Erase cycle

It is possible to check if the internal write, program or erase operation is completed, by

polling the dedicated register bits of the Read Status Register (RDSR) or Read Flag Status

Register (FSR).

When the Program or Erase cycle is performed with the VPP, the device temporarily goes in

single I/O SPI mode. The protocol became again QIO-SPI as soon as the VPP pin voltage

goes low.

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N25Q128A11B1241F Datasheet(PDF) 30 Page - Micron Technology

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