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N25Q128A11B1241F Datasheet(PDF) 99 Page - Micron Technology

Part No. N25Q128A11B1241F
Description  128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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Maker  MICRON [Micron Technology]
Homepage  http://www.micron.com
Logo MICRON - Micron Technology

N25Q128A11B1241F Datasheet(HTML) 99 Page - Micron Technology

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N25Q128 - 1.8 V
Instructions
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Figure 28.
Sector Erase instruction sequence
9.1.19
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the
entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0)
bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 29.
Bulk Erase instruction sequence
24 Bit Address
C
DQ0
Sector_Erase
S
2
1
3456789
29 30 31
Instruction
0
23 22
2
0
1
MSB
C
DQ0
AI13743
S
2
1
34567
0
Instruction


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