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N25Q128A11B1241F Datasheet(PDF) 86 Page - Micron Technology

Part No. N25Q128A11B1241F
Description  128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

N25Q128A11B1241F Datasheet(HTML) 86 Page - Micron Technology

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Instructions
N25Q128 - 1.8 V
86/185
Figure 16.
Quad Input/ Output Fast Read instruction sequence
9.1.8
Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each
bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on Serial Data output (DQ1).
Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock
(C). The instruction sequence is shown in Figure 17.
The address is automatically incremented to the next higher address after each byte of data
is shifted out.
There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the
Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read. All other
bytes outside the OTP area are “Don’t Care.”
The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read OTP (ROTP)
instruction issued while an Erase, Program or Write cycle is in progress, is rejected without
having any effect on the cycle that is in progress.
2
1
3
456789 10 11 12 13 14
0
Mode 3
Mode 0
C
DQ0
S
Instruction
Quad_IO_Fast_Read
15 16
24
21 22 23
40
4040
40
0
4
4
26
25
27
51
5151
DQ1
Don’t Care
Byte 1
51
1
5
5
73
3
7
7
73
7373
6
22
6
6
62
6262
DQ2
Don’t Care
Byte 2
Dummy (ex.: 10)
A23-16 A15-8 A7-0
DQ3
‘1’
IO switches from Input to Output


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