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N25Q128A11B1241F Datasheet(PDF) 45 Page - Micron Technology

Part No. N25Q128A11B1241F
Description  128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

N25Q128A11B1241F Datasheet(HTML) 45 Page - Micron Technology

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N25Q128 - 1.8 V
Volatile and Non Volatile Registers
45/185
6.5.1
P/E Controller Status bit
The bit 7 of the Flag Status register represents the Program/Erase Controller Status bit, It
indicates whether there is a Program/Erase internal cycle active. When P/E Controller
Status bit is Low (FSR<7>=0) the device is busy; when the bit is High (FSR<7>=1) the
device is ready to process a new command.
This bit has the same meaning of Write In Progress (WIP) bit of the standard SPI Status
Register, but with opposite logic: FSR<7> = not WIP
It's possible to make the polling instructions, to check if the internal modify operations are
finished, both on the Flag Status register bit 7 or on WIP bit of the Status Register.
6.5.2
Erase Suspend Status bit
The bit 6 of the Flag Status register represents the Erase Suspend Status bit, It indicates
that an Erase operation has been suspended or is going to be suspended.
The bit is set (FSR<6>=1) within the Erase Suspend Latency time, that is as soon as the
Program/Erase Suspend command (PES) has been issued, therefore the device may still
complete the operation before entering the Suspend Mode.
The Erase Suspend Status should be considered valid when the P/E Controller bit is high
(FSR<7>=1).
When a Program/Erase Resume command (PER) is issued the Erase Suspend Status bit
returns Low (FSR<6>=0)
6.5.3
Erase Status bit
The bit 5 of the Flag Status Register represents the Erase Status bit. It indicates an erase
failure or a protection error when an erase operation is issued.
When the Erase Status bit is High (FSR<5>=1) after an Erase failure that means that the
P/E Controller has applied the maximum pulses number to the portion to be erased and still
failed to verify that it has correctly erased.
The Erase Status bit should be read once the P/E Controller Status bit is High.
Table 8.
Flag Status Register
BIT
Description
Note
7
P/E Controller (not WIP)
Status
6
Erase Suspend
Status
5
Erase
Error
4
Program
Error
3
VPP
Error
2
Program Suspend
Status
1
Protection
Error
0
RESERVED


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