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MT46V32M16P-5BJ Datasheet(PDF) 33 Page - Micron Technology |
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MT46V32M16P-5BJ Datasheet(HTML) 33 Page - Micron Technology |
33 / 93 page PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN 33 ©2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Table 24: Electrical Characteristics and Recommended AC Operating Conditions (-75Z) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 37; 0°C ≤ T A ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V AC Characteristics -75Z Units Notes Parameter Symbol Min Max Access window of DQ from CK/CK# tAC –0.75 +0.75 ns CK high-level width tCH 0.45 0.55 tCK 31 Clock cycle time CL = 2.5 tCK (2.5) 7.5 13 ns 46 CL = 2 tCK (2) 7.5 13 ns 46 CK low-level width tCL 0.45 0.55 tCK 31 DQ and DM input hold time relative to DQS tDH 0.5 – ns 27, 32 DQ and DM input pulse width (for each input) tDIPW 1.75 – ns 32 Access window of DQS from CK/CK# tDQSCK –0.75 +0.75 ns DQS input high pulse width tDQSH 0.35 – tCK DQS input low pulse width tDQSL 0.35 – tCK DQS–DQ skew, DQS to last DQ valid, per group, per access tDQSQ – 0.5 ns 26, 27 WRITE command-to-first DQS latching transition tDQSS 0.75 1.25 tCK DQ and DM input setup time relative to DQS tDS 0.5 – ns 27, 32 DQS falling edge from CK rising – hold time tDSH 0.2 – tCK DQS falling edge to CK rising – setup time tDSS 0.2 – tCK Half-clock period tHP tCH,tCL – ns 35 Data-out High-Z window from CK/CK# tHZ – +0.75 ns 19, 43 Address and control input hold time (fast slew rate) tIH F 0.90 – ns Address and control input hold time (slow slew rate) tIH S 1– ns 15 Address and control input pulse width (for each input) tIPW 2.2 – ns Address and control input setup time (fast slew rate) tIS F 0.90 – ns Address and control input setup time (slow slew rate) tIS S 1– ns 15 Data-out Low-Z window from CK/CK# tLZ –0.75 – ns 19, 43 LOAD MODE REGISTER command cycle time tMRD 15 – ns DQ–DQS hold, DQS to first DQ to go non-valid, per access tQH tHP -tQHS – ns 26, 27 Data hold skew factor tQHS – 0.75 ns ACTIVE-to-READ with auto precharge command tRAP 20 – ns ACTIVE-to-PRECHARGE command tRAS 40 120,000 ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period tRC 65 – ns ACTIVE-to-READ or WRITE delay tRCD 20 – ns REFRESH-to-REFRESH command interval tREFC – 70.3 µs 24 Average periodic refresh interval tREFI – 7.8 µs 24 AUTO REFRESH command period tRFC 75 – ns 50 PRECHARGE command period tRP 20 – ns DQS read preamble tRPRE 0.9 1.1 tCK 44 DQS read postamble tRPST 0.4 0.6 tCK 44 ACTIVE bank a to ACTIVE bank b command tRRD 15 – ns Terminating voltage delay to VDD tVTD 0 – ns DQS write preamble tWPRE 0.25 – tCK DQS write preamble setup time tWPRES 0 – ns 21, 22 DQS write postamble tWPST 0.4 0.6 tCK 20 Write recovery time tWR 15 – ns |
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