MT46V32M16P-5BJ datasheet(80/93 Pages) MICRON

Part #	MT46V32M16P-5BJ

Description	Double Data Rate (DDR) SDRAM MT46V128M4 ??32 Meg x 4 x 4 banks MT46V64M8 ??16 Meg x 8 x 4 banks MT46V32M16 ??8 Meg x 16 x 4 banks

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Manufacturer	MICRON [Micron Technology]

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN

80

512Mb: x4, x8, x16 DDR SDRAM

Operations

Figure 44:

WRITE-to-READ – Interrupting

Notes:

1. DI b = data-in for column b; DO n = data-out for column n.

2. An interrupted burst of 4 is shown; two data elements are written.

3. One subsequent element of data-in is applied in the programmed order following DI b.

4. tWTR is referenced from the first positive CK edge after the last data-in pair.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

6. DQS is required at T2 and T2n (nominal case) to register DM.

7. If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ com-

mand will not mask these two data elements.

tDQSS (NOM)

CK

CK#

Command

WRITE

NOP

Address

Bank a,

Col b

Bank a,

Col n

READ

T0

T1

T2

T3

T2n

T4

T5

T5n

T1n

T6

T6n

tWTR

CL = 2

DQ

DQS

DM

DI

b

DO

n

tDQSS (MIN)

CL = 2

DQ

DQS

DM

DI

b

tDQSS (MAX)

CL = 2

DQ

DQS

DM

DI

b

DO

n

DO

n

Don’t Care

Transitioning Data

tDQSS

T3n

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MT46V32M16P-5BJ Datasheet(PDF) 80 Page - Micron Technology

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