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MT46V32M16P-5BJ Datasheet(PDF) 62 Page - Micron Technology |
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MT46V32M16P-5BJ Datasheet(HTML) 62 Page - Micron Technology |
62 / 93 page PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN 62 ©2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Operations Figure 27: Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK ≤ 3 READ During the READ command, the value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Note: For the READ commands used in the following illustrations, auto precharge is dis- abled. During READ bursts, the valid data-out element from the starting column address will be available following the CL after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK#). Figure 28 on page 64 shows the general timing for each possible CL setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. Detailed explanations of tDQSQ (valid data-out skew), tQH (data-out window hold), and the valid data window are depicted in Figure 36 on page 72 and Figure 37 on page 73. Detailed explanations of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to CK) are depicted in Figure 38 on page 74. Data from any READ burst may be concatenated or truncated with data from a subse- quent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 29 on page 65. A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive read data is illustrated in Figure 30 on page 66. Full-speed random read accesses within a page (or pages) can be performed, as shown in Figure 31 on page 67. Command BA0, BA1 ACTACT NOP tRRD tRCD CK CK# Bank x Bank y Address Row Row NOP RD/WR NOP Bank y Col NOP T0 T1 T2 T3 T4 T5 T6 T7 Don’t Care NOP |
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