MT46V32M16P-5BJ datasheet(60/93 Pages) MICRON

Part #	MT46V32M16P-5BJ

Description	Double Data Rate (DDR) SDRAM MT46V128M4 ??32 Meg x 4 x 4 banks MT46V64M8 ??16 Meg x 8 x 4 banks MT46V32M16 ??8 Meg x 16 x 4 banks

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Manufacturer	MICRON [Micron Technology]

Direct Link	http://www.micron.com

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60 / 93 page

PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN

60

512Mb: x4, x8, x16 DDR SDRAM

Operations

Operating Mode

The normal operating mode is selected by issuing an LMR command with bits A7–An

each set to zero and bits A0–A6 set to the desired values. A DLL reset is initiated by

issuing an LMR command with bits A7 and A9–An each set to zero, bit A8 set to one, and

bits A0–A6 set to the desired values. Although not required by the Micron device, JEDEC

specifications recommend that an LMR command resetting the DLL should always be

followed by an LMR command selecting normal operating mode.

All other combinations of values for A7–An are reserved for future use and/or test

modes. Test modes and reserved states should not be used, as unknown operation or

incompatibility with future versions may result.

Extended Mode Register

The extended mode register controls functions beyond those controlled by the mode

register; these additional functions are DLL enable/disable and output drive strength.

These functions are controlled via the bits shown in Figure 26 on page 61. The extended

mode register is programmed via the LMR command to the mode register (with BA0 = 1

and BA1 = 0) and will retain the stored information until it is programmed again or until

the device loses power. The enabling of the DLL should always be followed by an LMR

command to the mode register (BA0/BA1 = 0) to reset the DLL. The extended mode

register must be loaded when all banks are idle and no bursts are in progress, and the

controller must wait the specified time before initiating any subsequent operation.

Violating either requirement could result in an unspecified operation.

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II. This option

is intended for the support of the lighter load and/or point-to-point environments. The

selection of the reduced drive strength will alter the DQ and DQS pins from SSTL_2,

Class II drive strength to a reduced drive strength, which is approximately 54% of the

SSTL_2, Class II drive strength.

DLL Enable/Disable

When the part is running without the DLL enabled, device functionality may be altered.

The DLL must be enabled for normal operation. DLL enable is required during power-

up initialization and upon returning to normal operation after having disabled the DLL

for the purpose of debug or evaluation (when the device exits self refresh mode, the DLL

is enabled automatically). Anytime the DLL is enabled, 200 clock cycles with CKE HIGH

must occur before a READ command can be issued.

Table 37:

CAS Latency

Speed

Allowable Operating Clock Frequency (MHz)

CL = 2

CL = 2.5

CL = 3

-5B

75

≤ f ≤ 133

75

≤ f ≤ 167

133

≤ f ≤ 200

-6/-6T

75

≤ f ≤ 133

75

≤ f ≤ 167

–

-75E

75

≤ f ≤ 133

75

≤ f ≤ 133

–

-75Z

75

≤ f ≤ 133

75

≤ f ≤ 133

–

-75

75

≤ f ≤ 100

75

≤ f ≤ 133

–

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MT46V32M16P-5BJ Datasheet(PDF) 60 Page - Micron Technology

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