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FM93C56EMT8 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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FM93C56EMT8 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 16 page 1 www.fairchildsemi.com FM93CS56 Rev. C.1 July 2000 © 2000 Fairchild Semiconductor International FM93CS56 (MICROWIRE™ Bus Interface) 2048-Bit Serial EEPROM with Data Protect and Sequential Read General Description FM93CS56 is a 2048-bit CMOS non-volatile EEPROM organized as 128 x 16-bit array. This device features MICROWIRE interface which is a 4-wire serial bus with chipselect (CS), clock (SK), data input (DI) and data output (DO) signals. This interface is compat- ible to many of standard Microcontrollers and Microprocessors. FM93CS56 offers programmable write protection to the memory array using a special register called Protect Register. Selected memory locations can be protected against write by programming this Protect Register with the address of the first memory location to be protected (all locations greater than or equal to this first address are then protected from further change). Additionally, this address can be “permanently locked” into the device, making all future attempts to change data impossible. In addition this device features “sequential read”, by which, entire memory can be read in one cycle instead of multiple single byte read cycles. There are 10 instructions implemented on the FM93CS56, 5 of which are for memory operations and the remaining 5 are for Protect Register operations. This device is fabricated using Fairchild Semiconduc- tor floating-gate CMOS process for high reliability, high endurance and low power consumption. “LZ” and “L” versions of FM93CS56 offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space considerations. Functional Diagram Features I Wide V CC 2.7V - 5.5V I Programmable write protection I Sequential register read I Typical active current of 200µA 10 µA standby current typical 1 µA standby current typical (L) 0.1 µA standby current typical (LZ) I No Erase instruction required before Write instruction I Self timed write cycle I Device status during programming cycles I 40 year data retention I Endurance: 1,000,000 data changes I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP INSTRUCTION DECODER CONTROL LOGIC AND CLOCK GENERATORS COMPARATOR AND WRITE ENABLE HIGH VOLTAGE GENERATOR AND PROGRAM TIMER INSTRUCTION REGISTER ADDRESS REGISTER PROTECT REGISTER EEPROM ARRAY READ/WRITE AMPS DATA IN/OUT REGISTER 16 BITS DECODER 16 16 DATA OUT BUFFER PRE PE CS SK DI DO VSS VCC |
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