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FMS3115KRC Datasheet(PDF) 9 Page - Fairchild Semiconductor |
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FMS3115KRC Datasheet(HTML) 9 Page - Fairchild Semiconductor |
9 / 11 page PRODUCT SPECIFICATION FMS3110/3115 REV. 1.05 12/21/00 9 Applications Discussion Figure 5 illustrates a typical FMS3110/3115 interface cir- cuit. In this example, an optional 1.2 Volt bandgap reference is connected to the VREF output, overriding the internal volt- age reference source. Grounding It is important that the FMS3110/3115 power supply is well- regulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video sig- nals at the output of the circuit. The FMS3110/3115 has sep- arate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages (VDD) come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. Printed Circuit Board Layout Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following sug- gestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG) as short as possible and as far as possi- ble from all digital signals. The FMS3110/3115 should be located near the board edge, close to the analog out- put connectors. 2. Power plane for the FMS3110/3115 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the FMS3110/3115 is the same as that of the system's digital circuitry, power to the FMS3110/3115 should be decoupled with 0.1µF and 0.01µF capacitors and iso- lated with a ferrite bead. 3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. 4. If the digital power supply has a dedicated power plane layer, it should not be placed under the FMS3110/3115, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the FMS3110/3115 and its related analog circuitry can have an adverse effect on performance. 5. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. Related Products • FMS38XX Triple 8-bit 150 Msps D/A Converters • FMS9884A 3 x 8-bit 140 Ms/s A/D Converter Figure 5. Typical Interface Circuit R9-0 G9-0 B9-0 +5V 0.1 µF 10 µF VDD GND FMS31XX Triple 10-bit D/A Converter CLK SYNC BLANK RED PIXEL INPUT GREEN PIXEL INPUT BLUE PIXEL INPUT CLOCK SYNC BLANK COMP VREF RREF +5V 0.1 µF 0.1 µF 560 Ω 3.3k Ω (not required without external reference) LM185-1.2 (Optional) IOR IOG IOB 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω Z O=75Ω Red Green w/Sync Blue Z O=75Ω Z O=75Ω |
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