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AD9857/PCB Datasheet(PDF) 10 Page - Analog Devices |
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AD9857/PCB Datasheet(HTML) 10 Page - Analog Devices |
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10 / 40 page  AD9857 Rev. C | Page 10 of 40 Pin Number Mnemonic I/O Function 35, 37, 38, 43, 48, 54, 58, 64 AVDD 3.3 V Analog Power pin(s). 36, 39, 40, 42, 44, 47, 53, 56, 59, 61, 65 AGND Analog Ground pin(s). 45 IOUT O DAC Output pin. Normal DAC output current (analog). 46 IOUT O DAC Complementary Output pin. Complementary DAC output current (analog). 49 DAC_BP DAC Reference Bypass. Typically not used. 50 DAC_RSET I DAC Current Set pin. Sets DAC reference current. 55 PLL_FILTER O PLL Filter. R-C network for PLL filter. 60 DIFFCLKEN I Clock Mode Select pin. A logic high on this pin selects DIFFERENTIAL REFCLK input mode. A logic low selects the SINGLE-ENDED REFCLK input mode. 62 REFCLK I Reference Clock pin. In single-ended clock mode, this pin is the Reference Clock input. In differential clock mode, this pin is the positive clock input. 63 REFCLK I Inverted Reference Clock pin. In differential clock mode, this pin is the negative clock input. 66 DPD I Digital Power-Down pin. Assertion of this pin shuts down the digital sections of the device to conserve power. However, if selected, the PLL remains operational. 67 RESET I Hardware RESET pin. An active high input that forces the device into a predefined state. 68 PLL_LOCK O PLL Lock pin. Active high output signifying, in real time, when PLL is in lock state. 69 CIC_OVRFL O CIC Overflow pin. Activity on this pin indicates that the CIC Filters are in “overflow” state. This pin is typically low unless a CIC overflow occurs. 79 PDCLK/FUD I/O Parallel Data Clock/Frequency Update pin. When not in single-tone mode, this pin is an output signal that should be used as a clock to synchronize the acceptance of the 14-bit parallel data-words on Pins D13–D0. In single-tone mode, this pin is an input signal that synchronizes the transfer of a changed frequency tuning word (FTW) in the active profile (PSx) to the accumulator (FUD = frequency update signal). When profiles are changed by means of the PS–PS1 pins, the FUD does not have to be asserted to make the FTW active. 80 TxENABLE I When TxENABLE is asserted, the device processes the data through the I and Q data pathways; otherwise 0s are internally substituted for the I and Q data entering the signal path. The first data word accepted when the TxENABLE is asserted high is treated as I data, the next data word is Q data, and so forth. |
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