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M054LAN Datasheet(PDF) 25 Page - Nuvotem Talema

Part No. M054LAN
Description  ARM Cortex™-M0 32-BIT MICROCONTROLLER
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Maker  TALEMA [Nuvotem Talema]
Homepage  http://www.nuvotem.com
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M054LAN Datasheet(HTML) 25 Page - Nuvotem Talema

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M052/M054 Data Sheet
Publication Release Date: Mar 15, 2011
- 25 -
Revision V1.0
entry as illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main The Main stack pointer
Vector Number
Exception Entry Pointer using that Vector Number
Table 6–3 Vector Table Format
6.2.5.3
Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.


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