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FM93C56A Rev. C.1

SYNCHRONOUS DATA TIMING

CS

SK

DI

DO (Data Read)

DO (Status Read)

Valid Status

Valid

Input

Valid

Input

Valid

Output

Valid

Output

CS

SK

DI

DO

High - Z

Dummy

Bit

1

1

0

A1

A0

0

D1

D0

;;;;;;;;;;;;;;

;;;;;;;;;;;;;;

;;;

;;;

READ CYCLE (READ)

Address

Bits(8/9)

Star t

Bit

Opcode

Bits(2)

93C56A (ORG=1;

A

Address bits patter n -> x-A6-A5-A4-A3-A2-A1-A0

(x -> Don't Care, can be 0 or 1; A6-to-A0 -> User defined)

93C56A (ORG=0;

A

Address bits patter n -> x-A7-A6-A5-A4-A3-A2-A1-A0; User defined

(x -> Don't Care, can be 0 or 1; A7-to-A0 -> User defined)

A

n

A

n-1

D

n

Timing Diagrams

Address

Bits(8/9)

CS

SK

DI

DO

High - Z

WRITE ENABLE CYCLE (WEN)

Start

Bit

Opcode

Bits(2)

1

0

0

A1

A0

A

n

A

n-1

93C56A (ORG=1;

A

Address bits pattern -> 1-1-x-x-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1)

93C56A (ORG=0;

A

Address bits pattern -> 1-1-x-x-x-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1)