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FM24C32U Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FM24C32U Datasheet(HTML) 11 Page - Fairchild Semiconductor |
11 / 13 page 11 www.fairchildsemi.com FM24C32U Rev. A.1 S T O P A C K NO A C K Bus Activity: Master SDA Line 01 Bus Activity: EEPROM A C K A C K WORD ADDRESS (1) WORD ADDRESS (0) SLAVE ADDRESS SLAVE ADDRESS DATA A C K S T A R T S T A R T S T O P A C K Bus Activity: Master SDA Line Bus Activity: EEPROM A C K DATA n + x A C K DATA n + 2 DATA n +1 DATA n +1 A C K NO A C K Slave Address Read Operations Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read, and sequential read. Current Address Read Internally the FM24C32U contains an address counter that maintains the address of the last byte accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to "1," the FM24C32U issues an acknowledge and transmits the eight bit word. The master will not acknowledge the transfer but does generate a stop condition, and therefore the FM24C32U discontinues transmission. Refer Figure 6 for the sequence of address, acknowledge and data transfer. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to "1," the master must first perform a “dummy” write operation. The master issues the start condition, slave address with the R/W bit set to "0" and then the byte address. After the byte address acknowledge, the master imme- diately issues another start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the FM24C32U and then by the eight bit word. The master will not acknowledge the transfer but does generate the stop condition, and therefore the FM24C32U discontinues transmis- sion. Refer Figure 7 for the address, acknowledge, and data transfer sequence. Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The FM24C32U continues to output data for each acknowl- edge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condi- tion. The data output is sequential with the data from address n followed by the data from n + 1. The address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter "rolls over" to the beginning of the memory. FM24C32U continues to output data for each acknowledge received. Refer Figure 8 for the address, acknowledge, and data transfer sequence. Low VCC WRITE Lockout FM24C32U -“H” version offers low VCC write lockout feature to safeguard data whenever Vcc falls below 3.8V. Normally, the operating V CC for FM24C32U “H” version is 5V. However during system operation if the VCC reaches below 3.8V, then internally all write commands to the array are locked out. S T O P DATA A C K NO A C K S T A R T SLAVE ADDRESS Bus Activity: Master SDA Line Bus Activity: EEPROM 1 0 1 0 1 Current Address Read (Figure 6) Random Read (Figure 7) Sequential Read (Figure 8) |
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