4

Copyright © 2007 IXYS CORPORATION All rights reserved

IXDD504 / IXDE504

Unless otherwise noted, 4.5V

≤ V

All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

High input voltage

4.5V

≤ V

3

V

Low input voltage

4.5V

≤ V

0.8

V

Input voltage range

-5

V

Input current

0V

≤ V

-10

10

µA

High output voltage

V

Low output voltage

0.025

V

High state output

resistance

3

Ω

Low state output

resistance

2.5

Ω

Continuous output current

1

A

Rise time

10

ns

Fall time

9

ns

On-time propagation delay

23

ns

Off-time propagation delay

32

ns

Enable to output high

delay time

60

ns

Disable to high impedance

state delay time

120

ns

Power supply voltage

4.5

18

30

V

High impedance state

output leakage

200

µA

Power supply current

150

3

150

µA

mA

mA

Notes:

1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent

damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

2. The device is not intended to be operated outside of the Operating Ratings.

3. Electrical Characteristics provided are associated with the stated Test Conditions.

4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily

to highlight any specific performance limits within which the device is guaranteed to function.

1) The

θ

resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards

and the values would be lower with forced convection. For the 8-Lead DFN package, the

θ

on a PCB. The

θ

to the die, it is easy to reduce the

θ

easily, and potentially even lower. The

θ

construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management.

2)

θ

published for the PDIP and SOIC packages. The

θ

the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.

3) The

θ

The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the

U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was

given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the

DFNpackage.