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TLV5638MFKB Datasheet(PDF) 10 Page - Texas Instruments

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Part No. TLV5638MFKB
Description  2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TLV5638MFKB Datasheet(HTML) 10 Page - Texas Instruments

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APPLICATION INFORMATION
GENERAL FUNCTION
2 REF
CODE
0x1000
[V]
SERIAL INTERFACE
TMS320
DSP FSX
CLKX
DX
TLV5638
SCLK
DIN
CS
SPI
I/O
SCK
MOSI
TLV5638
SCLK
DIN
CS
Microwire
I/O
SK
SO
TLV5638
SCLK
DIN
CS
SERIAL CLOCK FREQUENCY AND UPDATE RATE
f
sclkmax +
1
t
whmin ) twlmin
+ 20 MHz
f
updatemax +
1
16 t
whmin ) twlmin
+ 1.25 MHz
TLV5638
SLAS225C – JUNE 1999 – REVISED JANUARY 2004
The TLV5638 is a dual 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial
interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer.
The output voltage (full scale determined by reference) is given by:
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power
on reset initially puts the internal latches to a defined state (all bits zero).
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI™, and Microwire™.
Figure 13. Three-Wire Interface
Notes on SPI™ and Microwire™: Before the controller starts the data transfer, the software has to generate a
falling edge on the pin connected to CS. If the word width is 8 bits (SPI™ and Microwire™), two write operations
must be performed to program the TLV5638. After the write operation(s), the holding registers or the control
register are updated automatically on the 16th positive clock edge.
The maximum serial clock frequency is given by:
The maximum update rate is:
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5638 has to be considered, too.
10


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