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NCP1015AP065G Datasheet(PDF) 8 Page - ON Semiconductor |
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NCP1015AP065G Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 22 page NCP1015 http://onsemi.com 8 0 2.00 4.00 6.00 8.00 Startup period Vcc 8.5V 7.5V Device internally pulses Figure 13. The Charge/Discharge Cycle over a 10 mF VCC Capacitor As one can see, the VCC capacitor shall be dimensioned to offer an adequate startup time, i.e. ensure regulation is reached before VCC crosses 7.5 V (otherwise the part enters the fault condition mode). If we know that DV = 1 V and ICC1 is 1.2 mA (for instance we selected a 11 W device switching at 65 kHz), then the VCC capacitor can be calculated using: C w ICC1 @ tstartup DV (eq. 1) Let’s suppose that the SMPS needs 10 ms to startup, then we will calculate C to offer a 15 ms period. As a result, C should be greater than 18 mF thus the selection of a 33 mF / 16 V capacitor is appropriate. Short Circuit Protection The internal protection circuitry involves a patented arrangement that permanently monitors the assertion of an internal error flag. This error flag is, in fact, a signal that instructs the controller that the internal maximum peak current limit is reached. This naturally occurs during the startup period (Vout is not stabilized to the target value) or when the optocoupler LED is no longer biased, e.g in a short−circuit condition or when the feedback network is broken. When the DSS normally operates, the logic checks for the presence of the error flag every time VCC crosses VCC(on). If the error flag is low (peak limit not active) then the IC works normally. If the error signal is active, then the NCP1015 immediately stops the output pulses, reduces its internal current consumption and does not allow the startup source to activate: VCC drops toward ground until it reaches the so−called latch−off level, where the current source activates again to attempt a new re−start. If the error has gone, the IC automatically resumes its operation. If the default is still there, the IC pulses during 8.5 V down to 7.5 V and enters a new latch−off phase. The resulting burst operation guarantees a low average power dissipation and lets the SMPS sustain a permanent short−circuit. Figure 14 presents the corresponding diagram: Figure 14. Simplified NCP1015 Short−Circuit Detection Circuitry − + 4 V FB Division Max Ip Flag VCC VCC(on) To Latch Reset Current Sense Information Clamp Active? The protection burst duty−cycle can easily be computed through the various timing events as portrayed by Figure 15: |
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