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CDCU877RHA Datasheet(PDF) 6 Page - Texas Instruments |
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CDCU877RHA Datasheet(HTML) 6 Page - Texas Instruments |
6 / 23 page www.ti.com Electrical Characteristics Timing Requirements CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D – JUNE 2005 – REVISED JULY 2007 over recommended operating free-air temperature range (unless otherwise noted) AVDD , PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VDDQ VIK Input II = 18 mA 1.7 -1.2 V IOH = –100 μA 1.7 to 1.9 VDDQ – 0.2 VOH High-level output voltage V IOH = –9 mA 1.7 1.1 IOL = 100 μA 0.1 VOL Low-level output voltage V IOL = 9 mA 1.7 0.6 IO(DL) Low-level output current, dissabled VO(DL) = 100 mV, OE = L 1.7 100 μA VOD Differential output voltage(1) 1.7 0.5 V CK, CK 1.9 ±250 II Input current μA OE, OS, 1.9 ±10 FBIN, FBIN IDD(LD) Supply current, static (IDDQ + IADD) CK and CK = L 1.9 500 μA CK and CK = 270 MHz. All outputs are open (not connected 1.9 135 Supply current, dynamic (IDDQ + IADD) to a PCB) IDD mA (see Note (2) for CPD calculation) All outputs are loaded with 2 pF 1.9 235 and 120- Ω termination resistor CK, CK 1.8 2 3 CI Input capacitance VI = VDD or GND FBIN, FBIN 1.8 2 3 pF CK, CK 1.8 0.25 CI(Δ) Change in input current VI = VDD or GND FBIN, FBIN 1.8 0.25 (1) VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition. (2) Total IDD = IDDQ + IADD = fCK × CPD × VDDQ, solving for CPD = (IDDQ + IADD)/(fCK × VDDQ) where fCK is the input frequency, VDDQ is the power supply, and CPD is the power dissipation capacitance. over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN MAX UNIT Clock frequency (operating)(1)(2) 10 400 MHz fCK Clock frequency (application)(1)(3) 160 340 MHz AVDD, VDD = 1.8 V ±0.1 V tDC Duty cycle, input clock 40% 60% tL Stabiliztion time (4) 12 μs (1) The PLL must be able to handle spread spectrum induced skew. (2) Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). (3) Application clock frequency indicates a range over which the PLL must meet all timing parameters. (4) Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. 6 Submit Documentation Feedback |
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