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BR93H86RFVM-2C Datasheet(PDF) 14 Page - Rohm |
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BR93H86RFVM-2C Datasheet(HTML) 14 Page - Rohm |
14 / 32 page BR93H86-2C 14/29 Datasheet Datasheet www.rohm.com 19.DEC.2012 Rev.002 TSZ02201-0R1R0G100050-1-2 © 2012 ROHM Co., Ltd. All rights reserved. TSZ22111・14・001 Timing Chart 1) Read Cycle (READ) (1) Start bit When data “1” is input for the first time after the rise of CS, this will be recognized as the start bit. And, even if multiple “0” are input after the rise of CS, the first “1” input will still be recognized as the start bit, and the following operation starts. This is common to all the commands that will be discussed hereafter . ○When the READ command is recognized, the data (16bit) of the selected address is output to serial. And at that moment, “0” (dummy bit) is output first, in sync with address bit A0 and with the rise of SK. Afterwhich, the main data is output in sync with the rise of SK. This IC has Address Auto Increment Function available only for READ command. wherein after executing READ command on the first selected address, the data of the next address is read. And this will continue in a sequential order of addresses with the use of a continuous SK clock input, and by keeping CS at “H” during auto-increment. 2) Write Cycle (WRITE) ○In this command, input 16-bit data (D15 to D0) are written to a designated address (A9 to A0). The actual write starts from the fall of CS, after D0 is sampled with SK clock (29 th clock from the start bit input), to the rise of the 30th clock. When STATUS is not detected (CS="L" fixed), WRITE time is 4ms (Max) in conformity with tE/W. And when STATUS is detected (CS="H"), all commands are not accepted for areas where "L" (BUSY) is output from D0. Therefore, do not input any command. Write is not made or canceled if CS starts to fall after the rise of the 30 th clock. Note: Take tSKH or more from the rise of the 29th clock to the fall of CS. 3) Write All Cycle (WRAL) ○In this command, input 16-bit data is written simultaneously to all addresses. Data is written in bulk at a write time of only 4ms (Max) in conformity with tE/W. When writing data to all addresses, designate each block by B2, B1, and B0, and execute write. Write time is Max.4ms. The actual write starts from the fall of CS, after D0 is sampled with SK clock (29 th clock from the start bit input), to the rise of the 30 th clock. If CS was ended after the rise of the 30th clock, command is canceled, and write is not completed. Note: Take tSKH or more from the rise of the 29th clock to the fall of CS. CS 1 2 1 4 High-Z 1 A9 A1 A0 0 D15 D14 D1 D15 D14 *1 *2 D0 SK DI DO 0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 29 30 0 3 5 tCS High-Z B1 READY BUSY tE/W DO 0D0 CS SK DI 12 01 5m STATUS n D1 B0 D15 1B2 0 tSV Figure 32 Write all Cycle Figure 31 Write Cycle Figure 30 Read Cycle tCS High-Z READY BUSY tE/W CS SK DI DO 12 4 A1 A0 0 STATUS n D0 D1 D15 D14 1Am 1 ~ ~ tSV ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 5 3 0 0 3 4 9 29 29 11 (2) The succeeding address’ data output (Auto-Increment Function) |
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