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FIN1104 Datasheet(PDF) 4 Page - Fairchild Semiconductor

Part No. FIN1104
Description  LVDS 4 Port High Speed Repeater
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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FIN1104 Datasheet(HTML) 4 Page - Fairchild Semiconductor

   
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4
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either Low-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: Passing criteria for maximum frequency is the output VOD > 200 mV and the duty cycle is 45% to 55% with all channels switching.
Note 7: Output loading is transmission line environment only; CL is < 1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions and
Propagation and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
Note A: All LVDS input pulses have frequency
= 10 MHz, t
R
or tF < = 0.5 ns
Note B: CL includes all probe and test fixture capacitances
FIGURE 3. Differential Driver Propagation Delay
and Transition Time Test Circuit
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 3)
tPLHD
Differential Output Propagation Delay
0.75
1.1
1.75
ns
LOW-to-HIGH
tPHLD
Differential Output Propagation Delay
0.75
1.1
1.75
ns
HIGH-to-LOW
RL = 100 Ω, CL = 5 pF,
tTLHD
Differential Output Rise Time (20% to 80%) VID = 200 mV to 450 mV,
0.29
0.4
0.58
ns
tTHLD
Differential Output Fall Time (80% to 20%)
VIC = |VID|/2 to VCC − (|VID|/2),
0.29
0.4
0.58
ns
tSK(P)
Pulse Skew |tPLH - tPHL|
Duty Cycle
= 50%,
0.02
0.2
ns
tSK(LH),
Channel-to-Channel Skew
See Figure 1 and Figure 3
0.02
0.15
ns
tSK(HL)
(Note 4)
0.02
tSK(PP)
Part-to-Part Skew (Note 5)
0.5
ns
fMAX
Maximum Frequency (Note 6)(Note 7)
400
800
MHz
tPZHD
Differential Output Enable Time
2.2
5
ns
from Z to HIGH
tPZLD
Differential Output Enable Time
2.5
5
ns
from Z to LOW
RL = 100 Ω, CL = 5 pF,
tPHZD
Differential Output Disable Time
See Figure 2 and Figure 3
1.8
5
ns
from HIGH to Z
tPLZD
Differential Output Disable Time
2.1
5
ns
from LOW to Z
tDJ
LVDS Data Jitter,
VID = 300 mV, PRBS = 2
23 - 1,
85
135
ps
Deterministic
VIC = 1.2V at 800 Mbps
tRJ
LVDS Clock Jitter,
VID = 300 mV,
2.1
3.5
ps
Random (RMS)
VIC = 1.2V at 400 MHz


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