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FIN1028 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. FIN1028
Description  3.3V LVDS 2-Bit High Speed Differential Receiver
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FIN1028 Datasheet(HTML) 1 Page - Fairchild Semiconductor

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© 2003 Fairchild Semiconductor Corporation
DS500503
www.fairchildsemi.com
March 2001
Revised June 2003
FIN1028
3.3V LVDS 2-Bit High Speed Differential Receiver
General Description
This dual receiver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100 mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
The FIN1028 can be paired with its companion driver, the
FIN1027, or any other LVDS driver.
Features
s Greater than 400Mbs data rate
s 3.3V power supply operation
s 0.4ns maximum differential pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Fail safe protection for open-circuit, shorted and
terminated conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Flow-through pinout simplifies PCB layout
s 8-Lead SOIC and 8-terminal MLP packages save space
Ordering Code:
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Function Table
H
= HIGH Logic Level
L
= LOW Logic Level
Fail Safe
= Open, Shorted, Terminated
Connection Diagrams
Pin Assignment for SOIC
(Top View)
Terminal Assignments for MLP
(Top Through View)
Order Number
Package Number
Package Description
FIN1028M
(Note 1)
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1028MPX
(Preliminary)
MLP08C
8-Terminal Molded Leadless Package (MLP) Dual, JEDEC MO-229, 2mm Square
[TAPE and REEL]
Pin Name
Description
ROUT1, ROUT2
LVTTL Data Outputs
RIN1+, RIN2+
Non-inverting LVDS Inputs
RIN1−, RIN2−
Inverting LVDS Inputs
VCC
Power Supply
GND
Ground
Input
Outputs
RIN+
RIN+
ROUT
LH
L
HL
H
Fail Safe Condition
H


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