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FIN1026 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. FIN1026
Description  3.3V LVDS 2-Bit High Speed Differential Receiver
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FIN1026 Datasheet(HTML) 1 Page - Fairchild Semiconductor

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© 2002 Fairchild Semiconductor Corporation
DS500784
www.fairchildsemi.com
June 2002
Revised June 2002
FIN1026
3.3V LVDS 2-Bit High Speed Differential Receiver
General Description
This dual receiver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
The FIN1026 can be paired with its companion driver, the
FIN1025, or any other LVDS driver.
Features
s Greater than 400Mbs data rate
s Flow-through pinout simplifies PCB layout
s 3.3V power supply operation
s 0.4ns maximum differential pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Fail safe protection for open-circuit, shorted and termi-
nated non-driven input conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s 14-Lead TSSOP package saves space
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Truth Table
H
= HIGH Logic Level
L
= LOW Logic Level
X
= Don’t Care
Z
= High Impedance
Fail Safe
= Open, Shorted, Terminated
Order Number
Package Number
Package Description
FIN1026MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Name
Description
ROUT1, ROUT2
LVTTL Data Outputs
RIN1+, RIN2+
Non-Inverting LVDS Inputs
RIN1−, RIN2−
Inverting LVDS Inputs
EN
Driver Enable Pin
EN
Inverting Driver Enable Pin
VCC
Power Supply
GND
Ground
NC
No Connect
Inputs
Outputs
EN
EN
RIN+
RIN−
ROUT
HL or Open
H
L
H
HL or Open
L
H
L
H
L or Open Fail Safe Condition
H
XH
X
X
Z
L or Open
X
X
X
Z


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