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FIN1018 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. FIN1018
Description  3.3V LVDS 1-Bit High Speed Differential Receiver
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FIN1018 Datasheet(HTML) 1 Page - Fairchild Semiconductor

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© 2002 Fairchild Semiconductor Corporation
DS500502
www.fairchildsemi.com
March 2001
Revised April 2002
FIN1018
3.3V LVDS 1-Bit High Speed Differential Receiver
General Description
This single receiver is designed for high speed intercon-
nects utilizing Low Voltage Differential Signaling (LVDS)
technology. The receiver translates LVDS levels, with a typ-
ical differential input threshold of 100 mV, to LVTTL signal
levels. LVDS provides low EMI at ultra low power dissipa-
tion even at high frequencies. This device is ideal for high
speed transfer of clock or data.
The FIN1018 can be paired with its companion driver, the
FIN1017, or with any other LVDS driver.
Features
s Greater than 400Mbs data rate
s 3.3V power supply operation
s 0.4ns maximum pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Fail safe protection for open-circuit, shorted and termi-
nated conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Flow-through pinout simplifies PCB layout
s 8-Lead SOIC and US-8 packages save space
Ordering Code:
Pin Descriptions
Function Table
H
= HIGH Logic Level
L
= LOW Logic Level
Fail Safe
= Open, Shorted, Terminated
Connection Diagrams
8-Lead SOIC
Pin Assignment for US-8 Package
TOP VIEW
Order Number
Package Number
Package Description
FIN1018M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
FIN1018MX
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
FIN1018K8X
MAB08A
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
Pin Name
Description
ROUT
LVTTL Data Output
RIN+
Non-inverting Driver Input
RIN−
Inverting Driver Input
VCC
Power Supply
GND
Ground
NC
No Connect
Input
Outputs
RIN+
RIN−
ROUT
LH
L
HL
H
Fail Safe Condition
H


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